//~ `New testbench
`timescale  1ns / 1ps

module tb_keyexp;

// keyexp Parameters
parameter PERIOD  = 10;


// keyexp Inputs
reg   clk                                  = 1 ;
reg   rst_n                                = 0 ;
reg   en                                   = 0 ;
reg   [3:0]  addr                          = 0 ;
reg   [127:0]  key                         = 0 ;
wire   [31:0]  sbox_out                   ;

// keyexp Outputs
wire  done                                 ;
wire  [127:0]  exp_key                     ;
wire  [31:0]  sbox_addr                    ;


initial
begin
    forever #(PERIOD/2)  clk=~clk;
end

initial
begin
    #(PERIOD*2) rst_n  =  1;
end

keyexp  u_keyexp (
    .clk                     ( clk                ),
    .rst_n                   ( rst_n              ),
    .en                      ( en                 ),
    .addr                    ( addr       [3:0]   ),
    .key                     ( key        [127:0] ),
    .sbox_out                ( sbox_out   [31:0]  ),

    .done                    ( done               ),
    .exp_key                 ( exp_key    [127:0] ),
    .sbox_addr               ( sbox_addr  [31:0]  )
);

sbox4  u_sbox4 (
    .cmd                     ( 3'b111   ),
    .in                      ( {96'd0,sbox_addr}    ),

    .out                     ( sbox_out   )
);

initial
begin   
    #(PERIOD * 2 + 3);
    key =  128'h2b7e151628aed2a6abf7158809cf4f3c;
    en = 1;
    #PERIOD;
    en = 0;

    @(negedge done);

    #(PERIOD * 100);

    for(addr=0;addr<11;addr=addr+1)begin
        #(PERIOD*5);
    end

    $stop;
end

endmodule